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74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
February 2001 Revised May 2005
74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
General Description
The LCX162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LCX162374 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The 26: series resistor in the output helps reduce output overshoot and undershoot. The LCX162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V-3.6V VCC specifications provided s Equivalent 26: series resistor on outputs s 7.0 ns tPD max (VCC
3.3V), 20 PA ICC max
s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r12 mA output drive (VCC
3.0V)
s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:
Human body model ! 2000V Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX162374GX (Note 2) 74LCX162374MEA (Note 3) 74LCX162374MTD (Note 3) Package Number BGA54A (Preliminary) MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2005 Fairchild Semiconductor Corporation
DS500442
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74LCX162374
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn CPn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Pin Assignment for FBGA Inputs CP1 Outputs I0-I7 H L X X O0-O7 H L O0 Z Outputs I8-I15 H L X X O8-O15 H L O0 Z OE1 L L L H Inputs CP2 (Top Thru View)

L X

L X
OE2 L L L H
H L X Z O0
HIGH Voltage Level LOW Voltage Level Immaterial High Impedance Previous O0 before HIGH-to-LOW of CP
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74LCX162374
Functional Description
The LCX162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCX162374
Absolute Maximum Ratings(Note 4)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V 3-STATE Output in HIGH or LOW State (Note 5) VI GND VO GND VO ! VCC V mA mA mA mA mA
0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 6)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V
r12 r8 r4 40
0 85 10
mA
qC
ns/V
't/'V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL IOL II IOZ Input Leakage Current 3-STATE Output Leakage Conditions VCC (V) 2.3 2.7 2.7 3.6 2.3 2.7 2.7 3.6 TA
40qC to 85qC
Max
Min 1.7 2.0
Units V
0.7 0.8 VCC 0.2 1.8 2.2 2.4 2.0 2.0 0.2 0.6 0.4 0.55 0.6 0.8
V
100 PA 4 mA 4 mA 6 mA 8 mA 12 mA
100 PA 4 mA 4 mA 6 mA 8 mA 12 mA
2.3 3.6 2.3 2.7 3.0 2.7 3.0 2.3 3.6 2.3 2.7 3.0 2.7 3.0 2.3 3.6 2.3 3.6
V
V
0 d VI d 5.5V 0 d VO d 5.5V VI VIH or VIL
r5.0 r5.0
PA PA
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74LCX162374
DC Electrical Characteristics
Symbol IOFF ICC Parameter Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input
(Continued)
VCC (V) 0 2.3 3.6 2.3 3.6 2.3 3.6 TA
Conditions VI or VO VI VIH 5.5V
40qC to 85qC
Max 10 20
Units
Min
PA PA PA
V CC or GND VCC 0.6V
3.6V d VI, VO d 5.5V (Note 7)
r20
500
'ICC
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA Symbol Parameter VCC CL Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 8) Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable time 170 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 1.0 1.0 7.0 7.0 6.9 6.9 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 7.3 7.3 7.1 7.1 6.2 6.2 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 8.4 8.4 9.0 9.0 7.2 7.2 3.3V r 0.3V 50 pF Max
40q to 85qC, RL
VCC CL Min 2.7V 50 pF Max
500: VCC CL Min 2.5V r 0.2V 30 pF Max MHz ns ns ns ns ns ns ns Units
Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30 pF, VIH 50 pF, VIH 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC Units V V Typical 0.35 0.25
0.35 0.25
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 20 Units pF pF pF
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74LCX162374
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V
trise and tfall
2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
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74LCX162374
Schematic Diagram Generic for LCX Family
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74LCX162374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary
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74LCX162374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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